Flash memory has become a very popular data storage apparatus nowadays. However, the data stored in flash memory may become erroneous due to occasional electrical noise, or due to random, non-repetitive bit arrangement in memory cell caused by the limited access speed as a result of the material characteristic of the flash memory. To maintain the correctness of the data stored in the logic memory cell, additional checking codes composed of bits are usually inserted into the data for locating and correcting the error bit(s). This data protection scheme is called error correction code (ECC) checking.
FIG. 1a illustrates a schematic view of the data structure of a flash memory in accordance with the conventional art. The flash memory 1 comprises a plurality of blocks 11, each block 11 comprises a plurality of pages 12 each composed of at least one sector 13, and each sector 13 comprises at least a data area 131 and a spare area 132. Because the minimum transmission data amount of the typical Integrated Device Electronic interface (IDE-ATA) is 512 bytes, the storing space of the data area 131 is generally 512 bytes and the storing space of the spare area 132 is 16 bytes.
FIG. 1b illustrates a schematic view of the data structure of the spare area 132 of the flash memory in accordance with the conventional art. The spare area 132 comprises bad memory information 141, ECC checking information 142, logic block address (LBA) information 143, split block logic sector address (SBLSA) information 144, and a redundant code 145 for ECC. The redundant code 145 is derived from the data by encoding with certain ECC scheme.
Generally, the storing space of the bad memory information 141 is one byte, which comprises bad block information and bad page information. The bad block information is for indicating whether this block is a defective block and the bad page information is for indicating whether this page is a defective page. The storing space of the ECC checking information 142 is one byte, and the ECC checking information 142 is for indicating whether the ECC checking should be executed. The storing space of the logic block address information 143 is two bytes. The storing space of the split block logic sector address information 144 is two bytes. The storing space of the ECC redundant code 145 is 10 bytes.
The flash memory in accordance with the conventional art is commonly encoded with a 4-bit ECC scheme to generate a 10-byte redundant code, which can then be stored in the data structure illustrated in FIG. 1b. Because data protection attracts much attention, using an ECC scheme with more bits becomes a trend of designing flash memory. However, since the redundant code of a 6-bit ECC scheme requires a storing space of 15 bytes, the redundant code of the 6-bit ECC scheme cannot be stored in the conventional data structure as illustrated in FIG. 1b. What is needed is then to dispose a data structure with stronger data protection and error correction ability in a limited storing space of the flash memory.